1. Field of the Invention
The present invention relates to an electron beam lithography apparatus, lithography method, and lithography program for drawing a circuit pattern of a semiconductor integrated circuit and a manufacturing method of a semiconductor device.
2. Description of the Related Art
In the manufacture of semiconductor elements, CMP (Chemical Mechanical Polishing), etching, and the like are used. These processes result in different processing shapes depending on the presence/absence of a surrounding pattern.
On the other hand, each semiconductor chip generally has a rectangular shape, and a silicon wafer has a circular shape. For this reason, when chips are to be laid out on the entire surface of a wafer, deficient chips are formed near the periphery of the wafer. Since these deficient chips do not function as chips, it is wasteful to expose them on the wafer.
However, under the present situation, in order to suppress variations of the processing shapes upon CMP or etching described above, these deficient chips are also drawn. This deficient chip drawing causes the following two problems in electron beam lithography.
First, a waste in time required to draw deficient chips is a serious problem in electron beam lithography which originally has a low throughput. Second, upon drawing deficient chips, a stage which mounts the wafer is irradiated with an electron beam. As a result, contaminations are accumulated on the stage.
Note that Jpn. Pat. Appln. KOKAI Publication No. 2000-269126 discloses the following technique. That is, upon drawing an invalid chip region as a region which suffers deficiency or insufficient chips to be drawn near the periphery of the wafer, a plurality of dummy patterns are exposed to have the same area density as a valid chip area, and a rectangle of a maximum shot size is set by a variable shaped electron beam.